Status Byte and Service Request Enable Register

The STB is already defined in IEEE 488.2. It provides a rough overview of the instrument status by collecting the pieces of information of the lower registers. It can thus be compared with the CONDition part of an SCPI register and assumes the highest level within the SCPI hierarchy. A special feature is that bit 6 acts as the sum bit of the remaining bits of the status byte.

The status byte is read out using the command "*STB?" or a serial poll.

The STB is linked to the SRE. The latter corresponds to the ENABle part of the SCPI registers in its function. Each bit of the STB is assigned a bit in the SRE. Bit 6 of the SRE is ignored. If a bit is set in the SRE and the associated bit in the STB changes from 0 to 1, a Service Request (SRQ) is generated on the GPIB bus, which triggers an interrupt in the controller if this is appropriately configured and can be further processed there.

The SRE can be set using command "*SRE" and read using "*SRE?".

Meaning of the bits used in the status byte

Bit no.	Meaning
2	Error Queue not empty
	This bit is set when an entry is made in the error queue. If this bit is enabled by the SRE, each entry of the error queue generates a Service Request. Thus an error can be recognized and specified in greater detail by polling the error queue. The poll provides an informative error message. This procedure is to be recommended since it considerably reduces the problems involved with GPIB bus control.
3	QUEStionable status sum bit
	This bit is set if an EVENt bit is set in the QUEStionable status register and the associated ENABle bit is set to 1. A set bit indicates a questionable instrument status, which can be specified in greater detail by polling the QUEStionable status register.
4	MAV-Bit (Message AVailable)
	This bit is set if a message is available in the output buffer which can be read. This bit can be used to enable data to be automatically read from the instrument to the controller (cf. annex D, program examples).
5	ESB bit
	Sum bit of the event status register. It is set if one of the bits in the event status register is set and enabled in the event status enable register. Setting of this bit indicates a serious error which can be specified in greater detail by polling the event status register.
6	MSS-Bit (Master Status Summary bit)
	This bit is set if the instrument triggers a service request. This is the case if one of the other bits of this register is set together with its mask bit in the service request enable register SRE.
7	OPERation status register sum bit
	This bit is set if an EVENt bit is set in the OPERation status register and the associated ENABle bit is set to 1. A set bit indicates that the instrument is just performing an action. The type of action can be queried by polling the OPERation status register.